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Datasheet File OCR Text:

Da t a S he et , V 0. 8 2 , O c t. 2 00 3
HYS6 4T320 00GDL ( 2 5 6 M B y t e ) HYS6 4T640 20GDL ( 5 1 2 M B y t e )
D D R 2 S ma l l O u t l i n e DIM M Mod ules
M em or y P r od uc t s
Never stop thinking.
HYS64T32000GDL HYS64T64020GDL Preliminary Datasheet Rev. 0.82 (10.03) 200-pin Small Outline DDR2 SDRAM Modules (SO-DIMMs) 256 MByte & 512 MByte Modules PC2-3200S /-4300S /-5300S
* 200-pin Non-ECC Unbuffered 8-Byte Dual-InLine DDR2 SDRAM Module for Notebooks and other application where small form factors are required. * One rank 32M x 64 and two ranks 64M x 64 organization * JEDEC standard Double Data Rate 2 Synchronous DRAMs (DDR2 SDRAM) with a single + 1.8 V ( 0.1 V) power supply * Built with 512Mb DDR2 SDRAMs in 84-ball FBGA chipsize packages * Programmable CAS Latencies (3, 4 & 5), Burst Length (4 & 8) and Burst Type * Auto Refresh (CBR) and Self Refresh * All inputs and outputs SSTL_1.8 compatible * OCD (Off-Chip Driver Impedance Adjustment) and ODT (On-Die Termination) * Serial Presence Detect with E2PROM * Low Profile Modules form factor: 67.60 mm x 30.00 mm (MO-224) * Based on JEDEC standard reference card layouts Raw Card "A" & "C"
* Performance:
Speed Grade Indicator Component Speed Grade Module Speed Grade Max. Clock Frequency @ CL = 3 Max. Clock Frequency @ CL = 4 & 5 -5 -3.7 -3 Unit
DDR2-400 DDR2-533 DDR2-667 PC2-3200 200 200 PC2-4300 200 266 PC2-5300 200 333 MHz MHz
1.0 Introduction The HYS64T32000GDL and HYS64T64020GDL are low profile Small-Outline DIMM modules (SODIMMs) with 30,0 mm height based on DDR2 technology. DIMMs are available as one rank 32M x 64 (256MB) and two ranks 64M x 64 (512MB) organisation and density, intended for mounting into 200 pin connector sockets. The memory array is designed with 512Mb Double Data Rate (DDR2) Synchronous DRAMs for Non-ECC applications. Decoupling capacitors are mounted on the PCB board. The DIMMs feature serial presence detect based on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer.
INFINEON Technologies
Rainer.Weidlich@Infineon.com
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10.03
HYS64T32000GDL / HYS64T64020GDL Small Outline DDR2 SDRAM-Modules
1.1 Ordering Information
Type & Partnumber PC2-3200: HYS64T32000GDL-5-A HYS64T64020GDL-5-A PC2-4300: HYS64T32000GDL-3.7-A PC2-4300S-44410-C one rank 256 MB SO-DIMM HYS64T64020GDL-3.7-A PC2-4300S-44410-A two ranks 512 MB SO-DIMM PC2-5300: HYS64T32000GDL-3-A HYS64T64020GDL-3-A PC2-5300S-44410-C one rank 256 MB SO-DIMM PC2-5300S-44410-A two ranks 512 MB SO-DIMM Non-ECC Non-ECC 512 MBit (x16) 512 MBit (x16) Non-ECC Non-ECC 512 MBit (x16) 512 MBit (x16) PC2-3200S-33310-C one rank 256 MB SO-DIMM PC2-3200S-33310-A two ranks 512 MB SO-DIMM Non-ECC Non-ECC 512 MBit (x16) 512 MBit (x16) Compliance Code Description ECC/ Non-ECC SDRAM Technology
Notes: 1. All part numbers end with a place code, designating the silicon die revision. Example: HYS 64T64020GDL-5-A, indicating Rev.A die are used for DDR2 SDRAM components. For all INFINEON DDR2 module and component nomenclature see section 8 of this datasheet. 2. The Compliance Code is printed on the module label and describes the speed grade, f.e. "PC2-4300S-44410-C", where 4300S means Small Outline DIMM modules with 4.26 GB/sec Module Bandwidth and "44410" means CAS latency = 4, trcd latency = 4 and trp latency = 4 using the latest JEDEC SPD Revision 1.0 and produced on the Raw Card "C".
1.2 Address Format
Density 256 MB 512 MB Module Organization 32M x 64 2 x 32M x 64 Memory Ranks 1 2 ECC/ Non-ECC Non-ECC Non-ECC # of SDRAMs 4 8 # of row/bank/ columns bits 13/2/10 13/2/10 Refresh 8k 8k Period Interval 64 ms 64 ms 7.8 s 7.8 s
1.3 Components on Modules
Density 256 MB 512 MB DRAM components reference datasheet HYB18T512160AC HYB18T512160AC DRAM Density 512 Mbit 512 Mbit DRAM Organisation 32Mb x 16 32Mb x 16
For a detailed description of all functionalities of the DRAM components on these modules see the referenced component datasheet
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HYS64T32000GDL / HYS64T64020GDL Small Outline DDR2 SDRAM-Modules
1.4 Pin Definition and Function
Pin Name A[12:0] A[9:0] A10/AP BA[1:0] CK[1:0] CK[1:0] RAS CAS WE CS[1:0] CKE[1:0] ODT[1:0] Description Row Address Inputs Column Address Inputs Column Address Input for AutoPrecharge SDRAM Bank Selects Clock input (positive line of differential pair) Clock input (negative line of differential pair) Row Address Strobe Column Address Strobe Read/Write Input Chip Selects Clock Enable Active termination control lines 1) Pin Name DQ[63:0] DQS[7:0] DQS[7:0] DM[7:0] SCL SDA SA[1:0] VDD VREF VSS VDDSPD NC Description Data Input/Output Data strobes Data strobes complement Data Masks Serial bus clock Serial bus data line slave address select Power (+ 1.8 V) I/O reference supply Ground EEPROM power supply no connect
1) Active termination only applies to DQ, DQS, DQS and DM signals 2) CS1, ODT1 and CKE1 are used on dual rank modules only
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HYS64T32000GDL / HYS64T64020GDL Small Outline DDR2 SDRAM-Modules
1.5 Pin Configuration
Pin # 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 Front Side VREF VSS DQ0 DQ1 VSS DQS0 DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1 DQS1 VSS DQ10 DQ11 VSS VSS DQ16 DQ17 VSS DQS2 Pin # 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 Back Side VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 VSS CK0 CK0 VSS DQ14 DQ15 VSS VSS DQ20 DQ21 VSS NC Pin # 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 Front Side DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 NC VSS DQ26 DQ27 VSS CKE0 VDD NC (BA2) VDD A12 A9 A8 VDD A5 A3 Pin# 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 Back Side DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3 DQS3 VSS DQ30 DQ31 VSS CKE1 VDD (A15) (A14) VDD A11 A7 A6 VDD A4 A2 Pin# 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 Front Side A1 VDD A10/AP BA0 WE VDD CAS CS1 VDD ODT1 VSS DQ32 DQ33 VSS DQS4 DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS Pin# 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 Back Side A0 VDD BA1 RAS CS0 VDD ODT0 (A13) VDD NC VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5 DQS5 VSS Pin # 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 Front Side DQ42 DQ43 VSS DQ48 DQ49 VSS NC VSS DQS6 DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SDA SCL Pin # 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 Back Side DQ46 DQ47 VSS DQ52 DQ53 VSS CK1 CK1 VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7 DQS7 VSS DQ62 DQ63 VSS SA0 SA1
199 VDDSPD 200
Pins 84, 85, 86 and 116 are not connected on this modules and are reserved for future modules
1.6 Pin Locations
Front View
1 2
39 40
41 42
(all odd pins) (all even pins)
199 200
Back View
200 pin SO-DIMM (MO-224)
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HYS64T32000GDL / HYS64T64020GDL Small Outline DDR2 SDRAM-Modules
1.7 Unbuffered DIMM Input/Output Functional Description
Symbol
CK[1:0], CK[1:0] CKE[1:0] CS[1:0]
Type
Input Input Input Input Input Input Input
Polarity
Function
The system clock inputs. All address and command lines are sampled on the cross point of Cross point the rising edge of CK and the falling edge of CK. Active High Activates the SDRAM clock signals when high and deactivates when lo. By deactivating the clocks, CKE low initiates the Power Down Mode or the Self Refresh Mode
Enables the associated SDRAM command decoder when low and disables decoder when Active Low high. When decoder is disabled, new commands are ignored and previous operations continue. This signal provides for external rank selection on systems with multiple ranks. DQ, DQS and Active High When high, termination resistance is enabled for allSet (EMRS). DM pins, assuming this function is enabled in the Extended mode Register Active Low When sampled at the positive edge of the clock, RAS, CAS and WE define the operation to be executed by the SDRAM. DM is an input mask signal for write data. Input data is masked when DM is sampled high Active High coincident with that input data during a write access. DM is samples on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. Selects which internal SDRAM memory bank is activated During Bank Activate command cycle, Address defines the row address. During a Read or Write command cycle, Address defines the column address. In addition to the column address, A10(=AP) is used to invoke Auto-Precharge operation at the end of the burst read or write cycle. If AP is high, Auto Precharge is selected and BA[1:0] defines the bank to be precharged. If AP is low, Auto-Precharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA[1:0] to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA[1:0]. If AP is low, BA[1:0] are used to define which bank to precharge. Data Input /Output pins.
ODT[1:0] RAS, CAS, WE DM[7:0] BA[1:0]
A[12:0]
Input
-
DQ[63:0]
I/O
-
DQS[7:0], DQS[7:0]
I/O
The data strobes, associated with one data byte, source with data transfer. In Write mode, the data strobe is sourced by the controller and is centered in the data window. In Read mode the data strobe is sources by the DDR2 SDRAM and is sent at the leading edge of the Cross point data window. DQS signals are complements, and timing is relative to the crosspoint of respective DQS and DQS. If the module is to be operated in single ended strobe mode, all DQS signals must be tied on the system board to VSS and DDR2 SDRAM mode registers programmed appropriately. These signals are tied at the system planar to either VSS or VDDSPD to configure the serial SPD EEPROM address range This bidirectional pin is used to transfer data into and out of the SPD EEPROM. A resistor maybe connected from the SDA bus line to VDDSPD on the system planar to act as a pullup. This signal is used to clock data into the SPD EEPROM. A resistor maybe connected from the SCL bus line to VDDSPD on the system planar to act as a pull-up. Power and ground for the DDR SDRAM input buffers and core logic. Reference voltage for the SSTL-18 inputs. Serial EEPROM positive power supply, wired to a separated power pin at the connector which supports from 1.7 Volt to 3.6 Volt.
SA[2:0] SDA SCL VDD, VSS VREF VDDSPD
Input I/O Input Supply Supply Supply
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HYS64T32000GDL / HYS64T64020GDL Small Outline DDR2 SDRAM-Modules
2.0 Block Diagrams 2.1 One Rank 32M x64 DDR2 SDRAM SO - DIMM Module (x16 components) HYS64T32000GDL on Raw Card C
CS0
3.0+/- 5% CS CS
DQS0 DQS0 DM0
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
DQS1 DQS1 DM1
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
LDQS LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/0 14 I/O 15
DQS4 DQS4 DM4
D0
DQS5 DQS5 DM5
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
LDQS LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/ O 12 I/O 13 I/0 14 I/O 15
D2
DQS2 DQS2 DM2
DQS3 DQS3 DM3
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
LDQS LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/ O 12 I/O 13 I/0 14 I/O 15
CS
DQS6 DQS6 DM6
D1
DQS7 DQS7 DM7
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
LDQS LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/0 14 I/O 15
CS
D3
VDDSPD
EEPROM D0 - D3 (VDD&VDDQ) D0 - D3 D0 - D3
Serial PD SDA SCL WP A0 A1 A2
Clock Wiring Clock Input CK0, CK0 CK1, CK1 SDRAMs 2 SDRAMs 2 SDRAMs
VDD VREF V SS
SA0 SA1
BA0, BA1 A0 - A12 RAS CAS WE CKE0 ODT0
3.0+/- 5% BA0, BA1 : SDRAMs D0 - D3 A0 - A12 : SDRAMs D0 - D3 RAS : SDRAMs D0 - D3 CAS : SDRAMs D0 - D3 WE CKE ODT : SDRAMs D0 - D3 : SDRAMs D0 - D3 : SDRAMs D0 - D3
DQ-to-I/O wiring may be changed within a byte DQ/DQS/DQS/DM/CKE/CS relationships must be maintained as shown DQ/DQS/DQS/DM resistors are 22 +/- 5% Address and control resistors are 3.0 +/- 5%
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HYS64T32000GDL / HYS64T64020GDL Small Outline DDR2 SDRAM-Modules
Block Diagram 2.2 Two Ranks 64M x 64 DDR2 SDRAM SO - DIMM Modules (x16 components) HYS64T64020GDL on Raw Card A
CS1 CS0 DQS0 DQS0 DM0
3.0+/- 5%
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
DQS1 DQS1 DM1
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
LDQS LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/0 14 I/O 15
CS
D0
LDQS LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/0 14 I/O 15
CS
DQS4 DQS4 DM4
D4
DQS5 DQS5 DM5
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
LDQS LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/0 14 I/O 15
CS
D2
LDQS LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/0 14 I/O 15
CS
D6
DQS2 DQS2 DM2
DQS3 DQS3 DM3
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
LDQS LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/ O 12 I/O 13 I/0 14 I/O 15
CS
D1
LDQS LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/ O 12 I/O 13 I/0 14 I/O 15
CS
DQS6 DQS6 DM6
D5
DQS7 DQS7 DM7
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
LDQS LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/0 14 I/O 15
CS
D3
LDQS LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/0 14 I/O 15
CS
D7
VDDSPD
EEPROM D0 - D7 (VDD & VDDQ) D0 - D7 D0 - D7
Serial PD SDA SCL WP A0 A1 A2
Clock Wiring Clock Input CK0, CK0 CK1, CK1 SDRAMs 4 SDRAMs 4 SDRAMs
VDD VREF V SS
SA0 SA1
BA0, BA1 A0 - A12 RAS CAS WE CKE0 CKE1 ODT0 ODT1
BA0, BA1 : SDRAMs D0 - D3 A0 - A12 : SDRAMs D0 - D3 RAS : SDRAMs D0 - D3 CAS : SDRAMs D0 - D3 WE CKE CKE ODT ODT : SDRAMs D0 - D3 : SDRAMs D0 - D3 : SDRAMs D4 - D7 : SDRAMs D0 - D3 : SDRAMs D4 - D7
DQ-to-I/O wiring may be changed within a byte DQ/DQS/DQS/DM/CKE/CS relationships must be maintained as shown DQ/DQS/DQS/DM resistors are 22 +/- 5% Address and control resistors are 3.0 +/- 5%
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HYS64T32000GDL / HYS64T64020GDL Small Outline DDR2 SDRAM-Modules
3.0 Absolute Maximum Ratings
Parameter Symbol Limit Values min. Voltage on any pins relative to VSS Voltage on VDD relative to VSS Voltage on VDD Q relative to VSS Storage temperature range VIN, VOUT VDD VDDQ TSTG - 0.5 - 1.0 - 0.5 -55 max. 2.3 2.3 2.3 +100
o
Unit
V V
C
Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
3.1 Operating Temperature Range
Parameter Symbol Limit Values min. DIMM Module Operating Temperature Range (ambient) DRAM Component Case Temperature Range TOPR TCASE 0 0 max. +65 +95
o o
Unit
Notes
C C 1-4
1. DRAM Component Case Temperature is the surface temperature in the center on the top side of any of the DRAMs. For measurement conditions, please refer to the JEDEC document JESD51-2. 2. Within the DRAM Component Case Temperature range all DRAM specification will be supported. 3. Above 85oC DRAM case temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 s. 4. Self-Refresh period is hard-coded in the DRAMs and therefore it is imperative that the system ensures the DRAM is below 85oC case temperature before initiating self-refresh operation.
3.2 Supply Voltage Levels and DC Operating Conditions (SSTL_1.8)
Parameter Symbol min. Device Supply Voltage Output Supply Voltage Input Reference Voltage EEPROM Supply Voltage DC Input Logic High DC Input Logic Low Input Leakage Current Output Leakage Current
1 2 3
Limit Values nom. 1.8 1.8 0.5 x VDDQ - - - max. 1.9 1.9 0.51 x VDDQ 3.6 VDDQ + 0.3 VREF - 0.125 5 5
Unit
Notes
VDD VDDQ VREF VDDSPD VIH (DC) VIL (DC) IIL IOL
1.7 1.7 0.49 x VDDQ 1.7 VREF + 0.125 - 0.30 -5 -5
V V V V V V A A
1) 2)
3) 3)
Under all conditions, VDDQ must be less than or equal to VDD Peak to peak AC noise on VREF may not exceed 2% VREF (DC).VREF is also expected to track noise variations in VDDQ. For any pin under test input of 0 V VIN VDDQ + 0.3 V. Values are shown per DDR2-SDRAM component
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HYS64T32000GDL / HYS64T64020GDL Small Outline DDR2 SDRAM-Modules
4.0 IDD Specifications and Conditions 4.1 256MByte SO-DIMM Module HYS64T32000GDL (1 rank, 4 components x16)
256 MByte HYS64T32000GDL Symbol Parameter / Condition IDD0 IDD1 IDD2P IDD2N IDD2Q
Operating Current Operating Current Precharge PD Standby Current Precharge Standby Current Precharge Quiet Standby Current
PC2-3200 "-5" typ. 201 239 7,1 65 49 26
tbd.
PC2-4300 "-3.7" typ. 216 260 9,4 87 65 35
tbd.
PC2-5300 "-3" typ. 237 286 11,8 109 81 43
tbd.
max. 241 287 9,9 78 68 37
tbd.
max. 259 312 13,1 104 90 49
tbd.
max. 284 343 16,5 131 113 61
tbd.
Unit Note 1 mA mA mA mA mA mA mA mA mA mA mA mA mA mA
1 1 1 1 1 1 1 1 1 1 1 1 1
IDD3P(0) Active PD Standby Current IDD3P(1) LP Active PD Standby Current IDD3N IDD4R IDD4W IDD5B IDD5D IDD6 IDD7
Active Standby Current Operating Current Burst Read Operating Current Burst Write Auto-Refresh Current (tRFCmin.) Auto-Refresh Current (tREFI) Low-Power Self-Refresh Current Operating Current
97 253 269 385
tbd.
117 304 323 462
tbd.
127 312 331 404
tbd.
153 374 397 485
tbd.
158 372 395 419
tbd.
189 447 474 503
tbd.
5 569
8 671
5 616
8 726
5 679
8 801
Notes: 1) Calculated values from component data. ODT disabled. IDD1, IDD4R, and IDD7 are defined with the outputs disabled.
4.2 512 MByte SO-DIMM Module HYS64T64020GDL (2 ranks, 8 components x16)
512 MByte HYS64T64020GDL Symbol Parameter / Condition IDD0 IDD1 IDD2P IDD2N IDD2Q
Operating Current Operating Current Precharge PD Standby Current Precharge Standby Current Precharge Quiet Standby Current
PC2-3200 "-5" typ. 208 246 14,1 131 97 52
tbd.
PC2-4300 "-3.7" typ. 226 269 18,8 174 129 69
tbd.
PC2-5300 "-3" typ. 249 298 23,5 218 162 87
tbd.
max. 251 297 19,8 157 136 73
tbd.
max. 273 325 26,3 207 181 97
tbd.
max. 301 360 32,9 261 227 122
tbd.
Unit Note mA 1, 2 mA mA mA mA mA mA mA mA mA mA mA mA mA
1, 2 1, 3 1, 3 1, 3 1, 3 1,3 1, 3 1, 2 1, 2 1, 2 1, 3 1, 3 1, 2
IDD3P(0) Active PD Standby Current IDD3P(1) LP Active PD Standby Current IDD3N IDD4R IDD4W IDD5B IDD5D IDD6 IDD7
Active Standby Current Operating Current Burst Read Operating Current Burst Write Auto-Refresh Current (tRFCmin.) Auto-Refresh Current (tREFI) Low-Power Self-Refresh Current Operating Current
195 261 276 392
tbd.
234 314 333 472
tbd.
254 321 341 413
tbd.
305 388 411 498
tbd.
315 384 407 431
tbd.
387 463 491 520
tbd.
10 576
16 681
10 625
16 740
10 691
16 818
Notes: 1) Calculated values from component data. ODT disabled. IDD1, IDD4R, and IDD7 are defined with the outputs disabled. 2) The other rank is in IDD2P Precharge Power-Down Standby Current mode 3) Both ranks are in the same IDD current mode
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HYS64T32000GDL / HYS64T64020GDL Small Outline DDR2 SDRAM-Modules
4.3 IDD Measurement Conditions
(VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V)
Symbol
Parameter/Condition Operating Current - One bank Active - Precharge tCK = tCKmin., tRC = tRCmin., tRAS = tRASmin., CKE is HIGH, CS is high between valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING. Operating Current - One bank Active - Read - Precharge IOUT = 0 mA, BL = 4, tCK = tCKmin., tRC = tRCmin., tRAS = tRASmin.,tRCD = tRCDmin.,AL = 0, CL = CLmin.; CKE is HIGH, CS is high between valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING. Precharge Power-Down Current: All banks idle; CKE is LOW; tCK = tCKmin.; Other control and address inputs are STABLE, Data bus inputs are FLOATING. Precharge Standby Current: All banks idle; CS is HIGH; CKE is HIGH; tCK = tCKmin.; Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING. Precharge Quiet Standby Current: All banks idle; CS is HIGH; CKE is HIGH; tCK = tCKmin.; Other control and address inputs are STABLE, Data bus inputs are FLOATING. Active Power-Down Current: All banks open; tCK = tCKmin., CKE is LOW; Other control and address inputs are STABLE, Data bus inputs are FLOATING. MRS A12 bit is set to "0" (Fast Power-down Exit); Active Power-Down Current: All banks open; tCK = tCKmin., CKE is LOW; Other control and address inputs are STABLE, Data bus inputs are FLOATING. MRS A12 bit is set to "1" (Slow Power-down Exit); Active Standby Current: All banks open; tCK = tCKmin.; tRAS = tRASmax; tRP = tRPmin.,CKE is HIGH; CS is high between valid commands. Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING. Operating Current - Burst Read: All banks open; Continuous burst reads; BL = 4;AL = 0, CL = CLmin.; tCK = tCKmin.; tRAS = tRASmax., tRP = tRPmin.; CKE is HIGH, CS is high between valid commands. Address inputs are SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0mA. Operating Current - Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CLmin.; tCK = tCKmin.; tRAS = tRASmax., tRP = tRPmin.; CKE is HIGH, CS is high between valid commands. Address inputs are SWITCHING; Data Bus inputs are SWITCHING; Burst Auto-Refresh Current: tCK = tCKmin., Refresh command every tRFC = tRFCmin. interval, CKE is HIGH, CS is HIGH between valid commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING. Distributed Auto-Refresh Current: tCK = tCKmin., Refresh command every tRFC = tREFI interval, CKE is LOW and CS is HIGH between valid commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING. Self-Refresh Current: CKE 0.2V; external clock off, CK and CK at 0V; Other control and address inputs are FLOATING, Data bus inputs are FLOATING. RESET = Low. IDD6 current values are guaranteed up to TCASE of 85oC max. All Bank Interleave Read Current: 1. All banks are being interleaved at minimum tRC without violating tRRD using a burst length of 4. Control and address bus inputs are STABLE during DESELECTS. Iout = 0mA.
IDD0 IDD1 IDD2P IDD2N IDD2Q IDD3P(0) IDD3P(1) IDD3N IDD4R IDD4W IDD5B IDD5D IDD6
IDD7
2. Timing pattern: - DDR2 -400: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D D - DDR2 -533: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D - DDR2 -667: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D 3. Legend: A = Activate, RA = Read with Auto-Precharge, D=DESELECT
Notes: 1. IDD specifications are tested after the device is properly initialized and IDD parameter are specified with ODT disabled. 2. Definitions for IDD: LOW is defined as VIN <= VIL(ac)max; HIGH is defined as VIN >= VIH(ac)min. STABLE is defined as inputs are stable at a HIGH or LOW level. FLOATING is defined as inputs are VREF = VDDQ / 2. SWITCHING is defined as: inputs are changing between HIGH and LOW every other clock (once per two cycles) for address and control signals, and inputs changing between HIGH and LOW every other clock (once per cycle) for DQ signals not including mask or strobes. 3. IDD1, IDD4R, and IDD7 current measurements are defined with the outputs disabled (Iout = 0 mA). To achieve this on module level the output buffers can be disabled using an EMRS(1) (Extended Mode Register Command) by setting A12 bit to HIGH. 3. For two rank modules: For all active current measurements the other rank is in Precharge Power-Down Mode IDD2P
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HYS64T32000GDL / HYS64T64020GDL Small Outline DDR2 SDRAM-Modules
4.3 IDD Measurement Conditions (cont'd)
For testing the IDD parameters, the following timing parameters are used:
-5 PC2-3200 3-3-3 CAS Latency Clock Cycle Time Active to Read or Write delay Active to Active / Auto-Refresh command period Active bank A to Active bank B command delay Active to Precharge Command Precharge Command Period Auto-Refresh to Active / Auto-Refresh command period Average periodic Refresh interval x16 CLmin tCKmin tRCDmin tRCmin tRRDmin tRASmin tRASmax tRPmin tRFCmin tREFI 3 5 15 60 10 45 70000 15 105 7.8 -3.7 PC2-4300 4-4-4 4 3.75 15 60 10 45 70000 15 105 7.8 -3 PC2-5300 4-4-4 4 3 12 57 10 45 70000 12 105 7.8 tCK ns ns ns ns ns ns ns ns s
Unit
Parameter
Symbol
4.4 ODT (On Die Termination) Current
The ODT function adds additional current consumption to the DDR2 SDRAM when enabled by the EMRS(1). Depending on address bits A6 & A2 in the EMRS(1) a "week" or "strong" termination can be selected. The current consumption for any terminated input pin, depends on the input pin is in tri-state or driving "0" or "1", as long a ODT is enabled during a given period of time.
ODT current per terminated pin:
EMRS(1) State Enabled ODT current per DQ added IDDQ current for ODT enabled; ODT is HIGH; Data Bus inputs are FLOATING Active ODT current per DQ added IDDQ current for ODT enabled; ODT is HIGH; worst case of Data Bus inputs are STABLE or SWITCHING. A6 = 0, A2 = 1 IODTO A6 = 1, A2 = 0 A6 = 0, A2 = 1 IODTT A6 = 1, A2 = 0 5 6 7.5 mA/DQ 2.5 10 3 12 3.75 15 mA/DQ mA/DQ min. 5 typ. 6 max. 7.5 Unit mA/DQ
note: For power consumption calculations the ODT duty cycle has to be taken into account
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HYS64T32000GDL / HYS64T64020GDL Small Outline DDR2 SDRAM-Modules
5.0 Electrical Characteristics & AC Timings
5.1 AC Timing Parameter by Speed Grade (Component level data, for reference only) -5 DDR2 -400
Min Max +600 +500 0.55 0.55 -600 -500 0.45 0.45
Symbol
Parameter
-3.7 DDR2 -533
Min -500 - 450 0.45 0.45 Max +500 + 450 0.55 0.55
-3 DDR2 -667
Min -450 -400 0.45 0.45 Max +450 +400 0.55 0.55
Unit
tAC tCH tCL tHP tCK tIS tIH tDH tDS tIPW tHZ tLZ
DQ output access time from CK / CK
ps ps tCK tCK
tDQSCK DQS output access time from CK / CK
CK, CK high-level width CK, CK low-level width Clock Half Period Clock cycle time CL = 3 CL = 4 & 5
min. (tCL, tCH) 5000 5000 600 600 400 400 0.6 0.35 tACmin 8000 8000 tACmax tACmax 350 450
min. (tCL, tCH) 5000 3750 600 600 350 350 0.6 0.35 tACmin 8000 8000 tACmax tACmax 300 400
min. (tCL, tCH) 5000 3000 tbd. tbd. tbd. tbd. 0.6 0.35 tACmin 8000 8000 tACmax tACmax tbd. tbd. WL +0.25 0.60 1.1 0.60 tCK tCK tCK tCK tCK ps tCK tCK tCK tCK ns ns ns ps ps ps ps ps ps tCK tCK ps ps ps ps
Address and control input setup time Address and control input hold time DQ and DM input hold time DQ and DM input setup time Control and Addr. input pulse width (each input)
tDIPW DQ and DM input pulse width (each input)
Data-out high-impedance time from CK / CK Data-out low-impedance time from CK
skew tDQSQ DQS-DQ & associated DQ signals) (for DQS
tQHS tQH
Data hold skew factor Data Output hold time from DQS
tHP-tQHS
WL -0.25 0.35 0.2 0.2 2 0 0.25 0.40 0.9 0.40 45 60 105
WL +0.25 0.60 1.1 0.60 -
tHP-tQHS
WL -0.25 0.35 0.2 0.2 2 0 0.25 0.40 0.9 0.40 45 60 105
WL +0.25 0.60 1.1 0.60 -
tHP-tQHS
WL -0.25 0.35 0.2 0.2 2 0 0.35 0.40 0.9 0.40 45 57 105
tDQSS Write command to 1st DQS latching transition tDQSL,H DQS input low (high) pulse width (write cycle) tDSS tDSH
DQS falling edge to CLK setup time (write cycle) DQS falling edge hold time from CLK (write cycle)
tMRD Mode register set command cycle time tWPRES Write preamble setup time tWPRE Write preamble tWPST Write postamble tRPRE Read preamble tRPST Read postamble tRAS tRC tRFC
Active to Precharge command Active to Active/Auto-refresh command period Auto-refresh to Active/Auto-refresh command period
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HYS64T32000GDL / HYS64T64020GDL Small Outline DDR2 SDRAM-Modules
Symbol
Parameter
-5 DDR2 -400
Min Max 12 7.8 3.9
-3.7 DDR2 -533
Min 15 15 10 2 15 WR+tRP 7.5 7.5 2 6 - AL 2 200 tRFC + 10 3 0 tIS+tCK +tIH Max 12 7.8 3.9
-3 DDR2 -667
Min 12 12 10 2 12 WR+tRP 7.5 7.5 2 6 - AL 2 200 tRFC + 10 3 0 tIS+tCK +tIH Max 12 7.8 3.9
Unit
tRCD tRP tRRD tCCD tWR tDAL tRTP tXARD tXARDS tXP
Active to Read or Write delay (with and without Auto-Precharge) delay Precharge command period Active bank A to Active bank B command x16 (2k page size)
15 15 10 2 15
ns ns ns tCK ns tCK ns ns tCK tCK tCK tCK ns tCK ns ns s
CAS A to CAS B Command Period Write recovery time
Auto precharge write recovery + precharge time WR+tRP 10 7.5 2 6 - AL 2 200 tRFC + 10 3 0 tIS+tCK +tIH -
tWTR Internal write to read command delay
Internal read to precharge command delay Exit power down to any valid command (other than NOP or Deselect) Exit active power-down mode to read command (slew exit, lower power) Exit precharge power-down to any valid command (other than NOP or Deselect)
tXSRD Exit Self-Refresh to read command tXSNR Exit Self-Refresh to non-read command tCKE tOIT
CKE minimum high and low pulse width OCD drive mode output delay
tDELAY Minimum time clocks remain ON after CKE asynchronously drops low
Periodic tREFI Average Interval Refresh 0 C - 85 C 85oC - 95oC
o o
1. For details and notes see the relevant INFINEON component datasheet 2. Timing definition and values for tis, tih, tds and tdh may change due to actual JEDEC work. This may also effect the SPD code for these parameters
5.2 ODT AC Electrical Characteristics and Operating Conditions (all speed bins
Symbol Parameter / Condition min. 2 DDR2-400/533 DDR2-667 tAC(min) tAC(min) tAC(min) + 2ns 2.5 tAC(min) tAC(min) + 2ns 3 8 max. 2 tAC(max) + 1 ns tAC(max) + 0.7 ns 2 tCK + tAC(max) + 1ns 2.5 tAC(max) + 0.6ns 2.5 tCK + tAC(max) + 1ns Units
tAOND tAON
ODT turn-on delay ODT turn-on
tCK ns ns tCK ns ns tCK tCK
tAONPD ODT turn-on (Power-Down Modes) tAOFD tAOF tAOFPD tANPD tAXPD
ODT turn-off delay ODT turn-off ODT turn-off delay (Power-Down Modes) ODT to Power Down Mode Entry Latency ODT Power Down Exit Latency
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HYS64T32000GDL / HYS64T64020GDL Small Outline DDR2 SDRAM-Modules
6.0 Serial Presence Detect Codes for SO-DIMM DIMM Modules
Byte# Description Speed Grade SPD Entry Value Hex Value HYS64T32000GDL HYS64T64020GDL 80 08 08 0D 0A 60 40 00 05 50 3D 30 60 50 tbd 00 82 10 00 00 0C 04 38 00 04 00 01 50 3D 30 60 50 tbd 50 60 3C 30 28 3C 30 2D 40 61
0 1 2 3 4 5 6 7 8 9
Number of SPD Bytes Total Bytes in Serial PD Memory Type Number of Row Addresses Number of Column Addresses Number of DIMM Banks, Package and Height Module Data Width Reserved Module Interface Levels Min. Clock Cycle Time at CAS Latency = 5
10
SDRAM Access Time from Clock at CL = 5
11 12 13 14 15 16 17 18 19 20 21 22 23
DIMM Configuration Type Refresh Rate/Type SDRAM Width, Primary Error Checking SDRAM Data Width Reserved Burst Length Supported Number of SDRAM Banks Supported CAS Latencies Reserved DIMM Type Information SDRAM Module Attributes SDRAM Device Attributes: General Min. Clock Cycle Time at CAS Latency = 4
24
SDRAM Access Time from Clock for CL = 4
25 26 27 28 29 30 31
Minimum Clock Cycle Time at CL = 3 Access Time from Clock at CL = 3 Minimum Row Precharge Time (tRP) Minimum Row Act. to Row Act. Delay (tRRD) Minimum RAS to CAS Delay (tRCD) Minimum RAS Pulse Width (tRAS) Module Density (per rank)
all all all all all all all all all -5 -3.7 -3 -5 -3.7 -3 all all all all all all all all all all all all -5 -3.7 -3 -5 -3.7 -3 all all -5 & -3.7 -3 all -5 & -3.7 -3 all
128 256 DDR2-SDRAM 13 10 1/2 x64 Undefined SSTL_1.8 5 ns 3.7 ns 3 ns 0.6 ns 0.5 ns tbd non-ECC 7.8 s / SR x16 non-ECC 4&8 4 5, 4, 3 Undefined SO-DIMM normal DIMM incl. weak driver 5 ns 3.7 ns 3 ns 0.6 ns 0.5 ns tbd 5 ns 0.6 ns 15 ns 12 ns 10 ns 15 ns 12 ns 45 ns 256 MB
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HYS64T32000GDL / HYS64T64020GDL Small Outline DDR2 SDRAM-Modules
Byte#
Description
Speed Grade
SPD Entry Value
Hex Value HYS64T32000GDL HYS64T64020GDL 60 tbd 60 tbd 40 35 tbd 40 35 tbd 3C 30 28 1E 1E 00 00 3C 39 69 80 23 1E tbd. 2D 28 tbd 00 10 tbd tbd tbd tbd tbd tbd C1000000
32 33 34
Address and Command Setup Time (tIS) Address and Command Hold Time (tIH) Data Input Setup Time (tDS)
35
Data Input Hold Time (tDH)
-5 & -3.7 -3 -5 & -3.7 -3 -5 -3.7 -3 -5 -3.7 -3 -5 & -3.7 -3 -5 -3.7 & -3 all all -5 & -3.7 -3 all all -5 -3.7 -3 -5 -3.7 -3
0.6 ns tbd 0.6 ns tbd 0.40 ns 0.35 ns tbd 0.40 ns 0.35 ns tbd 15 ns 12 ns 10 ns 7.5 ns 7.5 ns Undefined 60 ns 57 ns 105 ns 8 ns 0.35 ns 0.30 ns tbd 0.45 ns 0.40 ns tbd Revision 1.0
36 37 38 39 40 41 42 43 44
Write Recovery Time (tWR) Internal Write to Read Command delay (tWTR) Internal Read to Precharge delay (tRTP) Reserved Extension of Byte 41 tRC and Byte 42 tRFC Minimum Core Cycle Time (tRC) Min. Auto Refresh Command Cycle Time (tRFC) Maximum Clock Cycle Time tck Max. DQS-DQ Skew (tDQSQmax.)
45
Read Data Hold Skew Factor (tQHS)
46-61 62 63
Superset Information SPD Revision Checksum for Bytes 0 - 62
-5 -3.7 -3 -
64-71 72 73-90 91-92 93-94 95-98 99-127 128-255
Manufacturers JEDEC ID Code Module Assembly Location Module Part Number Module Revision Code Module Manufacturing Date Module Serial Number Manufacturer's Specific Data Open for Customer use
INFINEON Technologies
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HYS64T32000GDL / HYS64T64020GDL Small Outline DDR2 SDRAM-Modules
7.0 Package Outlines 7.1 Raw Card A Module Package DDR2 Small Outline DIMM Modules (SO-DIMM) Raw Card A two physical ranks, 8 components x16
67 .6 63 .6
0.13
0.15
3.8 m a x.
30.00
1 2 .1 5
39 1 1.4
41 4 7.4 4.2 2.7
1 99 2.4 5
1 0.1
2 .45 2 4
1 .0 40 42 2 00
2 .15
6
20
1.8 4
D e tail o f C o nta cts
D e ta il of C ha m fer
0.25
0.4 5 0 .6
0.2 -0.15
2.55
0 .2
-0.15
note: all outline dimensions and tolerances are in accordance with the JEDEC standard (MO-224)
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HYS64T32000GDL / HYS64T64020GDL Small Outline DDR2 SDRAM-Modules
7.2 Raw Card B Module Package DDR2 Small Outline DIMM Modules (SO-DIMMs) Raw Card C one physical rank, 4 components x16
67 .6 63 .6
0.13
0.15
tbd .m a x.
30.00
1 2 .1 5
39 1 1.4
41 4 7.4 4.2 2.7
1 99 2.4 5
1 0.1
2 .45 2 4
1 .0 40 42 2 00
2 .15
6
20
1.8 4
D e tail o f C o nta cts
D e ta il of C ha m fer
0.25
0.4 5 0 .6
0.2 -0.15
2.55
0 .2
-0.15
note: all outline dimensions and tolerances are in accordance with the JEDEC standard
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HYS64T32000GDL / HYS64T64020GDL Small Outline DDR2 SDRAM-Modules
8.0 Nomenclature (Modules & Components)
8.1 DDR2 DIMM Modules
1 Example:
1 2
INFINEON Prefix Module Data Width
2 64
3 T
4 64
5 0
6 2
7 8
7 0
8 G
9 DL
10 -5
11 -A
0 = standard G = standard module H = "green" module R = Registered DIMMs U = Unbuffered DIMMs DL = Small Outline DIMMs ML = MicroDIMM -5 = PC2-3200 (DDR2-400) -3.7 = PC2-4300 (DDR2-533) -3 = PC2-5300 (DDR2-667) A = 1st Generation B = 2nd Generation C = 3rd Generation
HYS
HYS for IFX DIMM Modules 64 = Non-ECC Modules 72 = ECC Modules T = DDR2
Product Variations Package
3
DRAM Technology
9
Module Type
4
Memory Density per I/O
64 = 64 Mb 128 = 128 Mb 256 = 256 Mb 0 = first revision 0 = One Rank 2 = Two Ranks
10
Speed Grade
5
Raw Card Revision Number of Memory Ranks
11
Die Revision
6
Multiplying "Memory Density per I/O" with "Module Data Width" and dividing by 8 for Non-ECC and 9 for ECC modules gives the overall module memory density in MBytes.
8.2 DDR2 Memory Components
1 Example: HYB
2 18
3 T
4 512
5 16
6 0
7 A
8 C
9 -5
1 2
INFINEON Component Prefix Power Supply Voltage
HYB for DRAM Components 18 = 1.8 V Power Supply
6 7
Product Variations Die Revision
0 = standard A = 1st Generation B = 2nd Generation C = 3rd Generation C = BGA package F = BGA package (lead and halogen free) -5 =...DDR2-400 -3.7 =.DDR2-533 -3 =...DDR2-667
3
DRAM Technology
T = DDR2 256 = 256 Mb 512 = 512 Mb 1G = 1024Mb 40 = x4, 4 data in/outputs 80 = x8, 8 data in/outputs 16 = x16, 16 data in/outputs
8 9
Package Type
4
Memory Density
Speed Grade
5
Memory Organisation
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HYS64T32000GDL / HYS64T64020GDL Small Outline DDR2 SDRAM-Modules
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